Reducing standby currents in a DRAM (Dynamic Random Access Memory) is particularly important in applications in which battery drive is assumed, including applications for mobile terminals. Of the standby currents in a DRAM, Icc2ps in particular is correlated with a leakage current which flows when the transistor is off, and is determined by a sub-threshold current (a current which flows before the channel turns on when a voltage is applied to the gate), a GIDL (Gate-Induced-Drain-Leakage current) and a junction leakage current. In particular, in a circuit (sub-word driver SWD) which drives a word line (sub-word line SWL) of a memory cell, the applied voltage Vpp is high (approximately 2.5 to 3 V), and therefore many leakage components are attributable to the GIDL. It is therefore important to reduce the GIDL in the sub-word driver SWD in order to lower the Icc2ps. In particular, in a state in which the sub-word line SWL is not selected, the OFF current of pMOS transistors in the sub-word driver SWD must be reduced. Suppressing the GIDL in the pMOS transistors is therefore directly coupled to reducing the Icc2ps.
With regard to the layout of a pMOS transistor in a conventional sub-word driver SWD, there are those that comprise U-shaped (C-shaped) gate electrodes 52a and 52b, first diffusion layers 51a and 51b provided inside the U-shapes of the gate electrodes 52a and 52b, a second diffusion layer 51c provided outside the U-shapes of the gate electrodes 52a and 52b, contact plugs 53a and 53b for bit lines, formed on the first diffusion layers 51a and 51b, and a contact plug 53c for a capacitor, formed on the second diffusion layer 51c (see FIG. 15 and FIG. 16; see FIG. 4 (b) and FIG. 20 of patent literature article 1, for example). In a standby current Icc2ps state, GND is applied to the second diffusion layer 51c serving as a source, Vkk is applied to the first diffusion layers 51a and 51b serving as drains, and Vpp is applied to the gate electrodes 52a and 52b and to a semiconductor substrate 101. Therefore a gate-source voltage Vgs=|Vpp| and a gate-drain voltage Vd=|Vpp|+|Vkk| are applied, and a GIDL is liable to occur in the standby current Icc2ps state.
With regard to the layout of pMOS transistors, attempts have been made to reduce GIDLs by providing, between the channel and the first diffusion layers 51a and 51b and the second diffusion layer 51c, an extension region 110 having the same conduction type as the first diffusion layers 51a and 51b and the second diffusion layer 51c, and having a lower impurity concentration than the first diffusion layers 51a and 51b and the second diffusion layer 51c, and adopting a halo structure in which a pocket-implant region 111 having the opposite conduction type to the first diffusion layers 51a and 51b and the second diffusion layer 51c and having a higher impurity concentration than that of a well is provided in a location that is deeper than the extension region 110, thereby relaxing the electric fields at the end portions of the gate electrodes 52a and 52b. Normally the extension region 110 is formed by ion implantation using a tilt angle (the angle at which the normal to the main surface of the semiconductor substrate 101 intersects the ion beam) of 0 degrees, and the pocket-implant region 111 is formed by ion implantation using a desired tilt angle.